From 2464dab3c47fde2134b3d0318bf123ec024f7d36 Mon Sep 17 00:00:00 2001 From: CoprDistGit Date: Mon, 5 Aug 2024 01:56:00 +0000 Subject: automatic import of edk2 --- ...itecturalMsr.h-add-defines-for-MTRR-cache.patch | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 0031-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch (limited to '0031-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch') diff --git a/0031-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch b/0031-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch new file mode 100644 index 0000000..1b439a4 --- /dev/null +++ b/0031-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch @@ -0,0 +1,41 @@ +From 3124da27dc460926f40477d247e021ceeabe0be3 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Tue, 30 Jan 2024 14:04:39 +0100 +Subject: [PATCH] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 55: OvmfPkg/Sec: Setup MTRR early in the boot process. +RH-Jira: RHEL-21704 +RH-Acked-by: Laszlo Ersek +RH-Commit: [2/4] a568bc2793d677462a2971aae9566a9bbc64b063 (kraxel.rh/centos-src-edk2) + +Reviewed-by: Michael D Kinney +Reviewed-by: Laszlo Ersek +Signed-off-by: Gerd Hoffmann +Message-ID: <20240130130441.772484-3-kraxel@redhat.com> + +patch_name: edk2-MdePkg-ArchitecturalMsr.h-add-defines-for-MTRR-cache.patch +present_in_specfile: true +location_in_specfile: 50 +--- + MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +index 756e7c86ec..08ba949cf7 100644 +--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h ++++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +@@ -2103,6 +2103,13 @@ typedef union { + #define MSR_IA32_MTRR_PHYSBASE9 0x00000212 + /// @} + ++#define MSR_IA32_MTRR_CACHE_UNCACHEABLE 0 ++#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING 1 ++#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH 4 ++#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED 5 ++#define MSR_IA32_MTRR_CACHE_WRITE_BACK 6 ++#define MSR_IA32_MTRR_CACHE_INVALID_TYPE 7 ++ + /** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to + #MSR_IA32_MTRR_PHYSBASE9 -- cgit v1.2.3