diff options
| author | CoprDistGit <infra@openeuler.org> | 2023-10-12 04:00:49 +0000 |
|---|---|---|
| committer | CoprDistGit <infra@openeuler.org> | 2023-10-12 04:00:49 +0000 |
| commit | c22f60e6e55f1bf300dd76d2222a93911f3b2bb2 (patch) | |
| tree | ef665e7018377f53612ac2751dcaea35a1c587b6 /5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch | |
| parent | 39a4763249cd6289e5019acfe0c98dbb169f5f2e (diff) | |
automatic import of xenopeneuler22.03_LTS
Diffstat (limited to '5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch')
| -rw-r--r-- | 5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch b/5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch new file mode 100644 index 0000000..7d2af46 --- /dev/null +++ b/5ec7dcf6-x86-dont-enter-C3-C6-with-errata.patch @@ -0,0 +1,68 @@ +# Commit b2d502466547e6782ccadd501b8ef1482c391f2c +# Date 2020-05-22 16:08:54 +0200 +# Author Roger Pau Monné <roger.pau@citrix.com> +# Committer Jan Beulich <jbeulich@suse.com> +x86/idle: prevent entering C3/C6 on some Intel CPUs due to errata + +Apply a workaround for errata BA80, AAK120, AAM108, AAO67, BD59, +AAY54: Rapid Core C3/C6 Transition May Cause Unpredictable System +Behavior. + +Limit maximum C state to C1 when SMT is enabled on the affected CPUs. + +Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> +Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> + +--- a/xen/arch/x86/cpu/intel.c ++++ b/xen/arch/x86/cpu/intel.c +@@ -297,6 +297,41 @@ static void early_init_intel(struct cpui + } + + /* ++ * Errata BA80, AAK120, AAM108, AAO67, BD59, AAY54: Rapid Core C3/C6 Transition ++ * May Cause Unpredictable System Behavior ++ * ++ * Under a complex set of internal conditions, cores rapidly performing C3/C6 ++ * transitions in a system with Intel Hyper-Threading Technology enabled may ++ * cause a machine check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang ++ * or unpredictable system behavior. ++ */ ++static void probe_c3_errata(const struct cpuinfo_x86 *c) ++{ ++#define INTEL_FAM6_MODEL(m) { X86_VENDOR_INTEL, 6, m, X86_FEATURE_ALWAYS } ++ static const struct x86_cpu_id models[] = { ++ /* Nehalem */ ++ INTEL_FAM6_MODEL(0x1a), ++ INTEL_FAM6_MODEL(0x1e), ++ INTEL_FAM6_MODEL(0x1f), ++ INTEL_FAM6_MODEL(0x2e), ++ /* Westmere (note Westmere-EX is not affected) */ ++ INTEL_FAM6_MODEL(0x2c), ++ INTEL_FAM6_MODEL(0x25), ++ { } ++ }; ++#undef INTEL_FAM6_MODEL ++ ++ /* Serialized by the AP bringup code. */ ++ if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && ++ x86_match_cpu(models) ) ++ { ++ printk(XENLOG_WARNING ++ "Disabling C-states C3 and C6 due to CPU errata\n"); ++ max_cstate = 1; ++ } ++} ++ ++/* + * P4 Xeon errata 037 workaround. + * Hardware prefetcher may cause stale data to be loaded into the cache. + * +@@ -323,6 +358,8 @@ static void Intel_errata_workarounds(str + + if (cpu_has_tsx_force_abort && opt_rtm_abort) + wrmsrl(MSR_TSX_FORCE_ABORT, TSX_FORCE_ABORT_RTM); ++ ++ probe_c3_errata(c); + } + + |