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| author | CoprDistGit <infra@openeuler.org> | 2023-10-12 04:00:49 +0000 |
|---|---|---|
| committer | CoprDistGit <infra@openeuler.org> | 2023-10-12 04:00:49 +0000 |
| commit | c22f60e6e55f1bf300dd76d2222a93911f3b2bb2 (patch) | |
| tree | ef665e7018377f53612ac2751dcaea35a1c587b6 /5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch | |
| parent | 39a4763249cd6289e5019acfe0c98dbb169f5f2e (diff) | |
automatic import of xenopeneuler22.03_LTS
Diffstat (limited to '5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch')
| -rw-r--r-- | 5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch b/5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch new file mode 100644 index 0000000..5305469 --- /dev/null +++ b/5ec82237-x86-extend-ISR-C6-workaround-to-Haswell.patch @@ -0,0 +1,33 @@ +# Commit b72d8870b5f68f06b083e6bfdb28f081bcb6ab3b +# Date 2020-05-22 20:04:23 +0100 +# Author Andrew Cooper <andrew.cooper3@citrix.com> +# Committer Andrew Cooper <andrew.cooper3@citrix.com> +x86/idle: Extend ISR/C6 erratum workaround to Haswell + +This bug was first discovered against Haswell. It is definitely affected. + +(The XenServer ticket for this bug was opened on 2013-05-30 which is coming up +on 7 years old, and predates Broadwell). + +Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> +Acked-by: Jan Beulich <jbeulich@suse.com> + +--- a/xen/arch/x86/acpi/cpu_idle.c ++++ b/xen/arch/x86/acpi/cpu_idle.c +@@ -572,8 +572,16 @@ bool errata_c6_workaround(void) + * registers), the processor may dispatch the second interrupt (from + * the IRR bit) before the first interrupt has completed and written to + * the EOI register, causing the first interrupt to never complete. ++ * ++ * Note: Haswell hasn't had errata issued, but this issue was first ++ * discovered on Haswell hardware, and is affected. + */ + static const struct x86_cpu_id isr_errata[] = { ++ /* Haswell */ ++ INTEL_FAM6_MODEL(0x3c), ++ INTEL_FAM6_MODEL(0x3f), ++ INTEL_FAM6_MODEL(0x45), ++ INTEL_FAM6_MODEL(0x46), + /* Broadwell */ + INTEL_FAM6_MODEL(0x47), + INTEL_FAM6_MODEL(0x3d), |