diff options
Diffstat (limited to '5ef6156a-x86-disallow-access-to-PT-MSRs.patch')
| -rw-r--r-- | 5ef6156a-x86-disallow-access-to-PT-MSRs.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/5ef6156a-x86-disallow-access-to-PT-MSRs.patch b/5ef6156a-x86-disallow-access-to-PT-MSRs.patch new file mode 100644 index 0000000..67e08c4 --- /dev/null +++ b/5ef6156a-x86-disallow-access-to-PT-MSRs.patch @@ -0,0 +1,49 @@ +# Commit bcdfbb70fca579baa04f212c0936b77919bdae11 +# Date 2020-06-26 16:34:02 +0100 +# Author Andrew Cooper <andrew.cooper3@citrix.com> +# Committer Andrew Cooper <andrew.cooper3@citrix.com> +x86/msr: Disallow access to Processor Trace MSRs + +We do not expose the feature to guests, so should disallow access to the +respective MSRs. For simplicity, drop the entire block of MSRs, not just the +subset which have been specified thus far. + +Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> +Reviewed-by: Wei Liu <wl@xen.org> +Reviewed-by: Jan Beulich <jbeulich@suse.com> + +--- a/xen/arch/x86/msr.c ++++ b/xen/arch/x86/msr.c +@@ -135,6 +135,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t + case MSR_TSX_FORCE_ABORT: + case MSR_TSX_CTRL: + case MSR_MCU_OPT_CTRL: ++ case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7): + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: +@@ -290,6 +291,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t + case MSR_TSX_FORCE_ABORT: + case MSR_TSX_CTRL: + case MSR_MCU_OPT_CTRL: ++ case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7): + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: +--- a/xen/include/asm-x86/msr-index.h ++++ b/xen/include/asm-x86/msr-index.h +@@ -182,6 +182,14 @@ + #define MSR_MCU_OPT_CTRL 0x00000123 + #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0) + ++#define MSR_RTIT_OUTPUT_BASE 0x00000560 ++#define MSR_RTIT_OUTPUT_MASK 0x00000561 ++#define MSR_RTIT_CTL 0x00000570 ++#define MSR_RTIT_STATUS 0x00000571 ++#define MSR_RTIT_CR3_MATCH 0x00000572 ++#define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) ++#define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) ++ + #define MSR_U_CET 0x000006a0 + #define MSR_S_CET 0x000006a2 + #define MSR_PL0_SSP 0x000006a4 |