Mock Version: 3.5 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/openeuler-22.03_LTS_SP1-aarch64-1686485065.555520/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=[]unshare_net=FalseprintOutput=True) Executing command: ['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'} and shell False /etc/profile.d/system-info.sh: line 55: ps: command not found Building target platforms: aarch64 Building for target aarch64 Wrote: /builddir/build/SRPMS/python-pythondata-cpu-rocket-0.0.post7146-1.src.rpm Child return code was: 0 Mock Version: 3.5 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/openeuler-22.03_LTS_SP1-aarch64-1686485065.555520/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=[]unshare_net=FalseprintOutput=True) Executing command: ['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'} and shell False /etc/profile.d/system-info.sh: line 55: ps: command not found Building target platforms: aarch64 Building for target aarch64 Wrote: /builddir/build/SRPMS/python-pythondata-cpu-rocket-0.0.post7146-1.src.rpm Child return code was: 0 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/openeuler-22.03_LTS_SP1-aarch64-1686485065.555520/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=[]unshare_net=FalseprintOutput=True) Executing command: ['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target aarch64 --nodeps /builddir/build/SPECS/python-pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'} and shell False /etc/profile.d/system-info.sh: line 55: ps: command not found Building target platforms: aarch64 Building for target aarch64 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.UOzYad + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf pythondata-cpu-rocket-0.0.post7146 + /usr/bin/gzip -dc /builddir/build/SOURCES/pythondata-cpu-rocket-0.0.post7146.tar.gz + /usr/bin/tar -xof - + STATUS=0 + '[' 0 -ne 0 ']' + cd pythondata-cpu-rocket-0.0.post7146 + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.S3j4O1 + umask 022 + cd /builddir/build/BUILD + cd pythondata-cpu-rocket-0.0.post7146 + CFLAGS='-O2 -g -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -fstack-protector-strong -grecord-gcc-switches -specs=/usr/lib/rpm/generic-hardened-cc1 -fasynchronous-unwind-tables -fstack-clash-protection' + LDFLAGS='-Wl,-z,relro -Wl,-z,now -specs=/usr/lib/rpm/generic-hardened-ld' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -s' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_rocket copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' creating build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog creating build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src creating build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc + sleep 1 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.w8BLVT + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 ++ dirname /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 + cd pythondata-cpu-rocket-0.0.post7146 + CFLAGS='-O2 -g -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -fstack-protector-strong -grecord-gcc-switches -specs=/usr/lib/rpm/generic-hardened-cc1 -fasynchronous-unwind-tables -fstack-clash-protection' + LDFLAGS='-Wl,-z,relro -Wl,-z,now -specs=/usr/lib/rpm/generic-hardened-ld' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 running install /usr/lib/python3.9/site-packages/setuptools/command/install.py:34: SetuptoolsDeprecationWarning: setup.py install is deprecated. Use build and pip and other standards-based tools. warnings.warn( running install_lib creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9 creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc creating /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.rom.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullQConfig.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.d -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullDConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x40.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.plusArgs -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.dts -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/README.md -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/__init__.py -> /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket byte-compiling /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/__init__.py to __init__.cpython-39.pyc writing byte-compilation script '/tmp/tmp0j1sdzs1.py' /usr/bin/python3 /tmp/tmp0j1sdzs1.py removing /tmp/tmp0j1sdzs1.py running install_egg_info running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' Copying pythondata_cpu_rocket.egg-info to /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7146-py3.9.egg-info running install_scripts + install -d -m755 /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64//usr/share/doc/python-pythondata-cpu-rocket + '[' -d doc ']' ~/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 ~/build/BUILD/pythondata-cpu-rocket-0.0.post7146 + '[' -d docs ']' + '[' -d example ']' + '[' -d examples ']' + pushd /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 + '[' -d usr/lib ']' + find usr/lib -type f -printf '"/%h/%f"\n' + '[' -d usr/lib64 ']' + '[' -d usr/bin ']' + '[' -d usr/sbin ']' + touch doclist.lst + '[' -d usr/share/man ']' ~/build/BUILD/pythondata-cpu-rocket-0.0.post7146 + popd + mv /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/filelist.lst . + mv /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/doclist.lst . + /usr/bin/find-debuginfo -j4 --strict-build-id -i --build-id-seed 0.0.post7146-1 --unique-debug-suffix -0.0.post7146-1.aarch64 --unique-debug-src-base python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 -S debugsourcefiles.list /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7146 find: 'debug': No such file or directory + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip + /usr/lib/rpm/brp-python-bytecompile /usr/bin/python 1 1 Bytecompiling .py files below /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64/usr/lib/python3.9 using /usr/bin/python3.9 + /usr/lib/rpm/brp-python-hardlink Processing files: python3-pythondata-cpu-rocket-0.0.post7146-1.noarch Provides: python-pythondata-cpu-rocket python3-pythondata-cpu-rocket = 0.0.post7146-1 python3.9dist(pythondata-cpu-rocket) = 0.0.post7146 python3dist(pythondata-cpu-rocket) = 0.0.post7146 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/sh python(abi) = 3.9 Processing files: python-pythondata-cpu-rocket-help-0.0.post7146-1.noarch warning: Empty %files file /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7146/doclist.lst Provides: python-pythondata-cpu-rocket-help = 0.0.post7146-1 python3-pythondata-cpu-rocket-doc Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 Wrote: /builddir/build/RPMS/python-pythondata-cpu-rocket-help-0.0.post7146-1.noarch.rpm Wrote: /builddir/build/RPMS/python3-pythondata-cpu-rocket-0.0.post7146-1.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.GwSpsC + umask 022 + cd /builddir/build/BUILD + cd pythondata-cpu-rocket-0.0.post7146 + /usr/bin/rm -rf /builddir/build/BUILDROOT/python-pythondata-cpu-rocket-0.0.post7146-1.aarch64 + RPM_EC=0 ++ jobs -p + exit 0 Child return code was: 0