%global _empty_manifest_terminate_build 0
Name: python-cocotb
Version: 1.7.2
Release: 1
Summary: cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
License: BSD
URL: https://www.cocotb.org
Source0: https://mirrors.nju.edu.cn/pypi/web/packages/55/d5/bc9081157720375d81977d4f69df94a4b4ff81163513b4bb57e28b232439/cocotb-1.7.2.tar.gz
Requires: python3-find-libpython
Requires: python3-cocotb-bus
%description
**cocotb** is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
[](https://docs.cocotb.org/en/latest/)
[](https://github.com/cocotb/cocotb/actions/workflows/build-test-dev.yml)
[](https://pypi.org/project/cocotb/)
[](https://gitpod.io/#https://github.com/cocotb/cocotb)
[](https://codecov.io/gh/cocotb/cocotb)
* Read the [documentation](https://docs.cocotb.org)
* Get involved:
* [Raise a bug / request an enhancement](https://github.com/cocotb/cocotb/issues/new) (Requires a GitHub account)
* [Join the mailing list](https://lists.librecores.org/listinfo/cocotb)
* [Join the Gitter chat room](https://gitter.im/cocotb)
## Installation
The current stable version of cocotb requires:
- Python 3.6+
- GNU Make 3+
- An HDL simulator (such as [Icarus Verilog](https://docs.cocotb.org/en/stable/simulator_support.html#icarus-verilog),
[Verilator](https://docs.cocotb.org/en/stable/simulator_support.html#verilator),
[GHDL](https://docs.cocotb.org/en/stable/simulator_support.html#ghdl) or
[other simulator](https://docs.cocotb.org/en/stable/simulator_support.html))
After installing these dependencies, the latest stable version of cocotb can be installed with pip.
```command
pip install cocotb
```
For more details on installation, including prerequisites,
see [the documentation](https://docs.cocotb.org/en/stable/install.html).
For details on how to install the *development* version of cocotb,
see [the preliminary documentation of the future release](https://docs.cocotb.org/en/latest/install_devel.html#install-devel).
**!!! Bus and Testbenching Components !!!**
The reusable bus interfaces and testbenching components have recently been moved to the [cocotb-bus](https://github.com/cocotb/cocotb-bus) package.
You can easily install these at the same time as cocotb by adding the `bus` extra install: `pip install cocotb[bus]`.
## Usage
As a first trivial introduction to cocotb, the following example "tests" a flip-flop.
First, we need a hardware design which we can test. For this example, create a file `dff.sv` with SystemVerilog code for a simple [D flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop). You could also use any other language a [cocotb-supported simulator](https://docs.cocotb.org/en/stable/simulator_support.html) understands, e.g. VHDL.
```systemverilog
// dff.sv
`timescale 1us/1ns
module dff (
output logic q,
input logic clk, d
);
always @(posedge clk) begin
q <= d;
end
endmodule
```
An example of a simple randomized cocotb testbench:
```python
# test_dff.py
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge
@cocotb.test()
async def test_dff_simple(dut):
""" Test that d propagates to q """
clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
cocotb.start_soon(clock.start()) # Start the clock
for i in range(10):
val = random.randint(0, 1)
dut.d.value = val # Assign the random value val to the input port d
await FallingEdge(dut.clk)
assert dut.q.value == val, "output q was incorrect on the {}th cycle".format(i)
```
A simple Makefile:
```make
# Makefile
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(shell pwd)/dff.sv
TOPLEVEL = dff
MODULE = test_dff
include $(shell cocotb-config --makefiles)/Makefile.sim
```
In order to run the test with Icarus Verilog, execute:
```command
make SIM=icarus
```
[](https://asciinema.org/a/317220)
For more information please see the [cocotb documentation](https://docs.cocotb.org/)
and [our wiki](https://github.com/cocotb/cocotb/wiki).
## Tutorials, examples and related projects
* the tutorial section [in the official documentation](https://docs.cocotb.org/)
* [cocotb-bus](https://github.com/cocotb/cocotb-bus) for pre-packaged testbenching tools and reusable bus interfaces.
* [cocotb-based USB 1.1 test suite](https://github.com/antmicro/usb-test-suite-build) for FPGA IP, with testbenches for a variety of open source USB cores
* [`cocotb-coverage`](https://github.com/mciepluc/cocotb-coverage), an extension for Functional Coverage and Constrained Randomization
* [`uvm-python`](https://github.com/tpoikela/uvm-python), an almost 1:1 port of UVM 1.2 to Python
* our wiki [on extension modules](https://github.com/cocotb/cocotb/wiki/Further-Resources#extension-modules-cocotbext)
* the list of [GitHub projects depending on cocotb](https://github.com/cocotb/cocotb/network/dependents)
%package -n python3-cocotb
Summary: cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
Provides: python-cocotb
BuildRequires: python3-devel
BuildRequires: python3-setuptools
BuildRequires: python3-pip
BuildRequires: python3-cffi
BuildRequires: gcc
BuildRequires: gdb
%description -n python3-cocotb
**cocotb** is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
[](https://docs.cocotb.org/en/latest/)
[](https://github.com/cocotb/cocotb/actions/workflows/build-test-dev.yml)
[](https://pypi.org/project/cocotb/)
[](https://gitpod.io/#https://github.com/cocotb/cocotb)
[](https://codecov.io/gh/cocotb/cocotb)
* Read the [documentation](https://docs.cocotb.org)
* Get involved:
* [Raise a bug / request an enhancement](https://github.com/cocotb/cocotb/issues/new) (Requires a GitHub account)
* [Join the mailing list](https://lists.librecores.org/listinfo/cocotb)
* [Join the Gitter chat room](https://gitter.im/cocotb)
## Installation
The current stable version of cocotb requires:
- Python 3.6+
- GNU Make 3+
- An HDL simulator (such as [Icarus Verilog](https://docs.cocotb.org/en/stable/simulator_support.html#icarus-verilog),
[Verilator](https://docs.cocotb.org/en/stable/simulator_support.html#verilator),
[GHDL](https://docs.cocotb.org/en/stable/simulator_support.html#ghdl) or
[other simulator](https://docs.cocotb.org/en/stable/simulator_support.html))
After installing these dependencies, the latest stable version of cocotb can be installed with pip.
```command
pip install cocotb
```
For more details on installation, including prerequisites,
see [the documentation](https://docs.cocotb.org/en/stable/install.html).
For details on how to install the *development* version of cocotb,
see [the preliminary documentation of the future release](https://docs.cocotb.org/en/latest/install_devel.html#install-devel).
**!!! Bus and Testbenching Components !!!**
The reusable bus interfaces and testbenching components have recently been moved to the [cocotb-bus](https://github.com/cocotb/cocotb-bus) package.
You can easily install these at the same time as cocotb by adding the `bus` extra install: `pip install cocotb[bus]`.
## Usage
As a first trivial introduction to cocotb, the following example "tests" a flip-flop.
First, we need a hardware design which we can test. For this example, create a file `dff.sv` with SystemVerilog code for a simple [D flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop). You could also use any other language a [cocotb-supported simulator](https://docs.cocotb.org/en/stable/simulator_support.html) understands, e.g. VHDL.
```systemverilog
// dff.sv
`timescale 1us/1ns
module dff (
output logic q,
input logic clk, d
);
always @(posedge clk) begin
q <= d;
end
endmodule
```
An example of a simple randomized cocotb testbench:
```python
# test_dff.py
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge
@cocotb.test()
async def test_dff_simple(dut):
""" Test that d propagates to q """
clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
cocotb.start_soon(clock.start()) # Start the clock
for i in range(10):
val = random.randint(0, 1)
dut.d.value = val # Assign the random value val to the input port d
await FallingEdge(dut.clk)
assert dut.q.value == val, "output q was incorrect on the {}th cycle".format(i)
```
A simple Makefile:
```make
# Makefile
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(shell pwd)/dff.sv
TOPLEVEL = dff
MODULE = test_dff
include $(shell cocotb-config --makefiles)/Makefile.sim
```
In order to run the test with Icarus Verilog, execute:
```command
make SIM=icarus
```
[](https://asciinema.org/a/317220)
For more information please see the [cocotb documentation](https://docs.cocotb.org/)
and [our wiki](https://github.com/cocotb/cocotb/wiki).
## Tutorials, examples and related projects
* the tutorial section [in the official documentation](https://docs.cocotb.org/)
* [cocotb-bus](https://github.com/cocotb/cocotb-bus) for pre-packaged testbenching tools and reusable bus interfaces.
* [cocotb-based USB 1.1 test suite](https://github.com/antmicro/usb-test-suite-build) for FPGA IP, with testbenches for a variety of open source USB cores
* [`cocotb-coverage`](https://github.com/mciepluc/cocotb-coverage), an extension for Functional Coverage and Constrained Randomization
* [`uvm-python`](https://github.com/tpoikela/uvm-python), an almost 1:1 port of UVM 1.2 to Python
* our wiki [on extension modules](https://github.com/cocotb/cocotb/wiki/Further-Resources#extension-modules-cocotbext)
* the list of [GitHub projects depending on cocotb](https://github.com/cocotb/cocotb/network/dependents)
%package help
Summary: Development documents and examples for cocotb
Provides: python3-cocotb-doc
%description help
**cocotb** is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
[](https://docs.cocotb.org/en/latest/)
[](https://github.com/cocotb/cocotb/actions/workflows/build-test-dev.yml)
[](https://pypi.org/project/cocotb/)
[](https://gitpod.io/#https://github.com/cocotb/cocotb)
[](https://codecov.io/gh/cocotb/cocotb)
* Read the [documentation](https://docs.cocotb.org)
* Get involved:
* [Raise a bug / request an enhancement](https://github.com/cocotb/cocotb/issues/new) (Requires a GitHub account)
* [Join the mailing list](https://lists.librecores.org/listinfo/cocotb)
* [Join the Gitter chat room](https://gitter.im/cocotb)
## Installation
The current stable version of cocotb requires:
- Python 3.6+
- GNU Make 3+
- An HDL simulator (such as [Icarus Verilog](https://docs.cocotb.org/en/stable/simulator_support.html#icarus-verilog),
[Verilator](https://docs.cocotb.org/en/stable/simulator_support.html#verilator),
[GHDL](https://docs.cocotb.org/en/stable/simulator_support.html#ghdl) or
[other simulator](https://docs.cocotb.org/en/stable/simulator_support.html))
After installing these dependencies, the latest stable version of cocotb can be installed with pip.
```command
pip install cocotb
```
For more details on installation, including prerequisites,
see [the documentation](https://docs.cocotb.org/en/stable/install.html).
For details on how to install the *development* version of cocotb,
see [the preliminary documentation of the future release](https://docs.cocotb.org/en/latest/install_devel.html#install-devel).
**!!! Bus and Testbenching Components !!!**
The reusable bus interfaces and testbenching components have recently been moved to the [cocotb-bus](https://github.com/cocotb/cocotb-bus) package.
You can easily install these at the same time as cocotb by adding the `bus` extra install: `pip install cocotb[bus]`.
## Usage
As a first trivial introduction to cocotb, the following example "tests" a flip-flop.
First, we need a hardware design which we can test. For this example, create a file `dff.sv` with SystemVerilog code for a simple [D flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop). You could also use any other language a [cocotb-supported simulator](https://docs.cocotb.org/en/stable/simulator_support.html) understands, e.g. VHDL.
```systemverilog
// dff.sv
`timescale 1us/1ns
module dff (
output logic q,
input logic clk, d
);
always @(posedge clk) begin
q <= d;
end
endmodule
```
An example of a simple randomized cocotb testbench:
```python
# test_dff.py
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge
@cocotb.test()
async def test_dff_simple(dut):
""" Test that d propagates to q """
clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
cocotb.start_soon(clock.start()) # Start the clock
for i in range(10):
val = random.randint(0, 1)
dut.d.value = val # Assign the random value val to the input port d
await FallingEdge(dut.clk)
assert dut.q.value == val, "output q was incorrect on the {}th cycle".format(i)
```
A simple Makefile:
```make
# Makefile
TOPLEVEL_LANG = verilog
VERILOG_SOURCES = $(shell pwd)/dff.sv
TOPLEVEL = dff
MODULE = test_dff
include $(shell cocotb-config --makefiles)/Makefile.sim
```
In order to run the test with Icarus Verilog, execute:
```command
make SIM=icarus
```
[](https://asciinema.org/a/317220)
For more information please see the [cocotb documentation](https://docs.cocotb.org/)
and [our wiki](https://github.com/cocotb/cocotb/wiki).
## Tutorials, examples and related projects
* the tutorial section [in the official documentation](https://docs.cocotb.org/)
* [cocotb-bus](https://github.com/cocotb/cocotb-bus) for pre-packaged testbenching tools and reusable bus interfaces.
* [cocotb-based USB 1.1 test suite](https://github.com/antmicro/usb-test-suite-build) for FPGA IP, with testbenches for a variety of open source USB cores
* [`cocotb-coverage`](https://github.com/mciepluc/cocotb-coverage), an extension for Functional Coverage and Constrained Randomization
* [`uvm-python`](https://github.com/tpoikela/uvm-python), an almost 1:1 port of UVM 1.2 to Python
* our wiki [on extension modules](https://github.com/cocotb/cocotb/wiki/Further-Resources#extension-modules-cocotbext)
* the list of [GitHub projects depending on cocotb](https://github.com/cocotb/cocotb/network/dependents)
%prep
%autosetup -n cocotb-1.7.2
%build
%py3_build
%install
%py3_install
install -d -m755 %{buildroot}/%{_pkgdocdir}
if [ -d doc ]; then cp -arf doc %{buildroot}/%{_pkgdocdir}; fi
if [ -d docs ]; then cp -arf docs %{buildroot}/%{_pkgdocdir}; fi
if [ -d example ]; then cp -arf example %{buildroot}/%{_pkgdocdir}; fi
if [ -d examples ]; then cp -arf examples %{buildroot}/%{_pkgdocdir}; fi
pushd %{buildroot}
if [ -d usr/lib ]; then
find usr/lib -type f -printf "/%h/%f\n" >> filelist.lst
fi
if [ -d usr/lib64 ]; then
find usr/lib64 -type f -printf "/%h/%f\n" >> filelist.lst
fi
if [ -d usr/bin ]; then
find usr/bin -type f -printf "/%h/%f\n" >> filelist.lst
fi
if [ -d usr/sbin ]; then
find usr/sbin -type f -printf "/%h/%f\n" >> filelist.lst
fi
touch doclist.lst
if [ -d usr/share/man ]; then
find usr/share/man -type f -printf "/%h/%f.gz\n" >> doclist.lst
fi
popd
mv %{buildroot}/filelist.lst .
mv %{buildroot}/doclist.lst .
%files -n python3-cocotb -f filelist.lst
%dir %{python3_sitearch}/*
%files help -f doclist.lst
%{_docdir}/*
%changelog
* Fri Apr 21 2023 Python_Bot <Python_Bot@openeuler.org> - 1.7.2-1
- Package Spec generated