%global _empty_manifest_terminate_build 0 Name: python-vhlsrs Version: 0.0.95 Release: 1 Summary: Package to automate the synthesis of vivado HLS components License: MIT License URL: https://gitlab.inria.fr/lforget/vhls_rs Source0: https://mirrors.nju.edu.cn/pypi/web/packages/7b/c6/3598fd718da593557659448efeecf1552d22b23ea4cd8ba45f205991443f/vhlsrs-0.0.95.tar.gz BuildArch: noarch Requires: python3-plumbum %description # vhlsrs It means Vivado HLS run synthesis. This package contains a script that runs vivado synthesis in a (somewhat) reproducible way. It also allow to search for the minimum pipeline depth design for a given clock period constrain. ## Usage ### Experience description The experience to run should be described in a .ini. A complete experiment description looks like : ``` [EXP_NAME] comp_path=path/to/component/file.cpp top_level_comp= Name of top level function period= clock period in ns (float) part= part code name (default is xc7k160tfbg484) standard= c++ standard to use. (default is c++11) includes=comma separated list of directories containing includes to use during the synthesis. optionnal. defines=Key=comma separated list of key=value preprocessor macro that will be defined during synthesis keep_env=True/False Should the synthesis environment be kept after the synthesis is performed. Default is False. ip_lib= Name of the ip library to use when exporting the ip (optionnal) ip_version= Version to use when exporting the ip (optionnal) ip_descr= description that will be exported along the vivado ip (optionnal) ip_vendor= vendor name for the exported vivado ip (optionnal) latency= ltency constraint for the initial design (optionnal) hdl= verilog|VHDL no_pipeline=True|False if true the design will not be pipelined (default false) no_inline=True|False if true the function call will not be inlined (default false) ctrl_hs=True|False Block protocol will be ap_ctrl_hs if true, ap_ctrl_none else. Default false. exp_type=hls|syn|impl until which phase is the experiment to be performed ``` ### Running a one shot synthesis `python -m vhlsrs impl [expdescr.ini]` will implement the experiments described in expdescr.ini either with a latency constraint if given or with the minimal latency estimated by the tool. ### Minimizing the latency As vivado HLS is sometimes not very good at timing estimation, it can lead to overpessimistic latency. the `python -m vhlsrs minimize [expdescr.ini]` will attempt to find the lowest pipeline depth that still respect the clock constraints by dichotomy. If a latency constraint is provided, it will start the exploration with a designed with this constraint. Otherwise, it will start the exploration with the latency estimated by the tool. %package -n python3-vhlsrs Summary: Package to automate the synthesis of vivado HLS components Provides: python-vhlsrs BuildRequires: python3-devel BuildRequires: python3-setuptools BuildRequires: python3-pip %description -n python3-vhlsrs # vhlsrs It means Vivado HLS run synthesis. This package contains a script that runs vivado synthesis in a (somewhat) reproducible way. It also allow to search for the minimum pipeline depth design for a given clock period constrain. ## Usage ### Experience description The experience to run should be described in a .ini. A complete experiment description looks like : ``` [EXP_NAME] comp_path=path/to/component/file.cpp top_level_comp= Name of top level function period= clock period in ns (float) part= part code name (default is xc7k160tfbg484) standard= c++ standard to use. (default is c++11) includes=comma separated list of directories containing includes to use during the synthesis. optionnal. defines=Key=comma separated list of key=value preprocessor macro that will be defined during synthesis keep_env=True/False Should the synthesis environment be kept after the synthesis is performed. Default is False. ip_lib= Name of the ip library to use when exporting the ip (optionnal) ip_version= Version to use when exporting the ip (optionnal) ip_descr= description that will be exported along the vivado ip (optionnal) ip_vendor= vendor name for the exported vivado ip (optionnal) latency= ltency constraint for the initial design (optionnal) hdl= verilog|VHDL no_pipeline=True|False if true the design will not be pipelined (default false) no_inline=True|False if true the function call will not be inlined (default false) ctrl_hs=True|False Block protocol will be ap_ctrl_hs if true, ap_ctrl_none else. Default false. exp_type=hls|syn|impl until which phase is the experiment to be performed ``` ### Running a one shot synthesis `python -m vhlsrs impl [expdescr.ini]` will implement the experiments described in expdescr.ini either with a latency constraint if given or with the minimal latency estimated by the tool. ### Minimizing the latency As vivado HLS is sometimes not very good at timing estimation, it can lead to overpessimistic latency. the `python -m vhlsrs minimize [expdescr.ini]` will attempt to find the lowest pipeline depth that still respect the clock constraints by dichotomy. If a latency constraint is provided, it will start the exploration with a designed with this constraint. Otherwise, it will start the exploration with the latency estimated by the tool. %package help Summary: Development documents and examples for vhlsrs Provides: python3-vhlsrs-doc %description help # vhlsrs It means Vivado HLS run synthesis. This package contains a script that runs vivado synthesis in a (somewhat) reproducible way. It also allow to search for the minimum pipeline depth design for a given clock period constrain. ## Usage ### Experience description The experience to run should be described in a .ini. A complete experiment description looks like : ``` [EXP_NAME] comp_path=path/to/component/file.cpp top_level_comp= Name of top level function period= clock period in ns (float) part= part code name (default is xc7k160tfbg484) standard= c++ standard to use. (default is c++11) includes=comma separated list of directories containing includes to use during the synthesis. optionnal. defines=Key=comma separated list of key=value preprocessor macro that will be defined during synthesis keep_env=True/False Should the synthesis environment be kept after the synthesis is performed. Default is False. ip_lib= Name of the ip library to use when exporting the ip (optionnal) ip_version= Version to use when exporting the ip (optionnal) ip_descr= description that will be exported along the vivado ip (optionnal) ip_vendor= vendor name for the exported vivado ip (optionnal) latency= ltency constraint for the initial design (optionnal) hdl= verilog|VHDL no_pipeline=True|False if true the design will not be pipelined (default false) no_inline=True|False if true the function call will not be inlined (default false) ctrl_hs=True|False Block protocol will be ap_ctrl_hs if true, ap_ctrl_none else. Default false. exp_type=hls|syn|impl until which phase is the experiment to be performed ``` ### Running a one shot synthesis `python -m vhlsrs impl [expdescr.ini]` will implement the experiments described in expdescr.ini either with a latency constraint if given or with the minimal latency estimated by the tool. ### Minimizing the latency As vivado HLS is sometimes not very good at timing estimation, it can lead to overpessimistic latency. the `python -m vhlsrs minimize [expdescr.ini]` will attempt to find the lowest pipeline depth that still respect the clock constraints by dichotomy. If a latency constraint is provided, it will start the exploration with a designed with this constraint. Otherwise, it will start the exploration with the latency estimated by the tool. %prep %autosetup -n vhlsrs-0.0.95 %build %py3_build %install %py3_install install -d -m755 %{buildroot}/%{_pkgdocdir} if [ -d doc ]; then cp -arf doc %{buildroot}/%{_pkgdocdir}; fi if [ -d docs ]; then cp -arf docs %{buildroot}/%{_pkgdocdir}; fi if [ -d example ]; then cp -arf example %{buildroot}/%{_pkgdocdir}; fi if [ -d examples ]; then cp -arf examples %{buildroot}/%{_pkgdocdir}; fi pushd %{buildroot} if [ -d usr/lib ]; then find usr/lib -type f -printf "/%h/%f\n" >> filelist.lst fi if [ -d usr/lib64 ]; then find usr/lib64 -type f -printf "/%h/%f\n" >> filelist.lst fi if [ -d usr/bin ]; then find usr/bin -type f -printf "/%h/%f\n" >> filelist.lst fi if [ -d usr/sbin ]; then find usr/sbin -type f -printf "/%h/%f\n" >> filelist.lst fi touch doclist.lst if [ -d usr/share/man ]; then find usr/share/man -type f -printf "/%h/%f.gz\n" >> doclist.lst fi popd mv %{buildroot}/filelist.lst . mv %{buildroot}/doclist.lst . %files -n python3-vhlsrs -f filelist.lst %dir %{python3_sitelib}/* %files help -f doclist.lst %{_docdir}/* %changelog * Mon May 15 2023 Python_Bot - 0.0.95-1 - Package Spec generated