diff options
Diffstat (limited to '0130-Backport-SME-aarch64-Add-a-Z-operand-modifier-for-SV.patch')
| -rw-r--r-- | 0130-Backport-SME-aarch64-Add-a-Z-operand-modifier-for-SV.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/0130-Backport-SME-aarch64-Add-a-Z-operand-modifier-for-SV.patch b/0130-Backport-SME-aarch64-Add-a-Z-operand-modifier-for-SV.patch new file mode 100644 index 0000000..bea41d9 --- /dev/null +++ b/0130-Backport-SME-aarch64-Add-a-Z-operand-modifier-for-SV.patch @@ -0,0 +1,49 @@ +From 8dc1eee26c61bea8aab62080bd961825142685f9 Mon Sep 17 00:00:00 2001 +From: Richard Sandiford <richard.sandiford@arm.com> +Date: Tue, 7 Nov 2023 15:22:57 +0000 +Subject: [PATCH 031/157] [Backport][SME] aarch64: Add a %Z operand modifier + for SVE registers + +Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f40eac535bd55192cf93daca16235efbcd91157a + +This patch adds a %Z operand modifier that prints registers as SVE z +registers. The SME patches need this, but so do Tamar's patches. +I'm separating this out to unblock those. + +We should probably document the [wxbhsdqZ] modifiers as +user-facing, but doing that for all of them is a separate patch. + +gcc/ + * config/aarch64/aarch64.cc (aarch64_print_operand): Add a %Z + modifier for SVE registers. +--- + gcc/config/aarch64/aarch64.cc | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc +index 3e83e48ec..fd1114b52 100644 +--- a/gcc/config/aarch64/aarch64.cc ++++ b/gcc/config/aarch64/aarch64.cc +@@ -11901,6 +11901,10 @@ sizetochar (int size) + 'N': Take the duplicated element in a vector constant + and print the negative of it in decimal. + 'b/h/s/d/q': Print a scalar FP/SIMD register name. ++ 'Z': Same for SVE registers. ('z' was already taken.) ++ Note that it is not necessary to use %Z for operands ++ that have SVE modes. The convention is to use %Z ++ only for non-SVE (or potentially non-SVE) modes. + 'S/T/U/V': Print a FP/SIMD register name for a register list. + The register printed is the FP/SIMD register name + of X + 0/1/2/3 for S/T/U/V. +@@ -12073,6 +12077,8 @@ aarch64_print_operand (FILE *f, rtx x, int code) + case 's': + case 'd': + case 'q': ++ case 'Z': ++ code = TOLOWER (code); + if (!REG_P (x) || !FP_REGNUM_P (REGNO (x))) + { + output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code); +-- +2.33.0 + |