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1 files changed, 213 insertions, 0 deletions
diff --git a/0158-Backport-SME-aarch64-Simplify-output-template-emissi.patch b/0158-Backport-SME-aarch64-Simplify-output-template-emissi.patch
new file mode 100644
index 0000000..6d50608
--- /dev/null
+++ b/0158-Backport-SME-aarch64-Simplify-output-template-emissi.patch
@@ -0,0 +1,213 @@
+From b51d3b1af24758534e5a8f3a52a56106b935c485 Mon Sep 17 00:00:00 2001
+From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+Date: Wed, 31 May 2023 11:23:23 +0100
+Subject: [PATCH 059/157] [Backport][SME] aarch64: Simplify output template
+ emission code for a few patterns
+
+Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=11bd9b1f8133fc07c267e6d1aee8b01e06c7a750
+
+If the output code for a define_insn just does a switch (which_alternative) with no other computation we can almost always
+replace it with more compact MD syntax for each alternative in a mult-alternative '@' block.
+This patch cleans up some such patterns in the aarch64 backend, making them shorter and more concise.
+No behavioural change intended.
+
+Bootstrapped and tested on aarch64-none-linux-gnu.
+
+gcc/ChangeLog:
+
+ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Rewrite
+ output template to avoid explicit switch on which_alternative.
+ (*aarch64_simd_mov<VQMOV:mode>): Likewise.
+ (and<mode>3): Likewise.
+ (ior<mode>3): Likewise.
+ * config/aarch64/aarch64.md (*mov<mode>_aarch64): Likewise.
+---
+ gcc/config/aarch64/aarch64-simd.md | 97 +++++++++---------------------
+ gcc/config/aarch64/aarch64.md | 42 ++++---------
+ 2 files changed, 40 insertions(+), 99 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index ef7fc4ecb..2d688edf5 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -122,28 +122,16 @@
+ "TARGET_FLOAT
+ && (register_operand (operands[0], <MODE>mode)
+ || aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
+-{
+- switch (which_alternative)
+- {
+- case 0: return "ldr\t%d0, %1";
+- case 1: return "str\txzr, %0";
+- case 2: return "str\t%d1, %0";
+- case 3:
+- if (TARGET_SIMD)
+- return "mov\t%0.<Vbtype>, %1.<Vbtype>";
+- return "fmov\t%d0, %d1";
+- case 4:
+- if (TARGET_SIMD)
+- return "umov\t%0, %1.d[0]";
+- return "fmov\t%x0, %d1";
+- case 5: return "fmov\t%d0, %1";
+- case 6: return "mov\t%0, %1";
+- case 7:
+- return aarch64_output_simd_mov_immediate (operands[1], 64);
+- case 8: return "fmov\t%d0, xzr";
+- default: gcc_unreachable ();
+- }
+-}
++ "@
++ ldr\t%d0, %1
++ str\txzr, %0
++ str\t%d1, %0
++ * return TARGET_SIMD ? \"mov\t%0.<Vbtype>, %1.<Vbtype>\" : \"fmov\t%d0, %d1\";
++ * return TARGET_SIMD ? \"umov\t%0, %1.d[0]\" : \"fmov\t%x0, %d1\";
++ fmov\t%d0, %1
++ mov\t%0, %1
++ * return aarch64_output_simd_mov_immediate (operands[1], 64);
++ fmov\t%d0, xzr"
+ [(set_attr "type" "neon_load1_1reg<q>, store_8, neon_store1_1reg<q>,\
+ neon_logic<q>, neon_to_gp<q>, f_mcr,\
+ mov_reg, neon_move<q>, f_mcr")
+@@ -158,29 +146,16 @@
+ "TARGET_FLOAT
+ && (register_operand (operands[0], <MODE>mode)
+ || aarch64_simd_reg_or_zero (operands[1], <MODE>mode))"
+-{
+- switch (which_alternative)
+- {
+- case 0:
+- return "ldr\t%q0, %1";
+- case 1:
+- return "stp\txzr, xzr, %0";
+- case 2:
+- return "str\t%q1, %0";
+- case 3:
+- return "mov\t%0.<Vbtype>, %1.<Vbtype>";
+- case 4:
+- case 5:
+- case 6:
+- return "#";
+- case 7:
+- return aarch64_output_simd_mov_immediate (operands[1], 128);
+- case 8:
+- return "fmov\t%d0, xzr";
+- default:
+- gcc_unreachable ();
+- }
+-}
++ "@
++ ldr\t%q0, %1
++ stp\txzr, xzr, %0
++ str\t%q1, %0
++ mov\t%0.<Vbtype>, %1.<Vbtype>
++ #
++ #
++ #
++ * return aarch64_output_simd_mov_immediate (operands[1], 128);
++ fmov\t%d0, xzr"
+ [(set_attr "type" "neon_load1_1reg<q>, store_16, neon_store1_1reg<q>,\
+ neon_logic<q>, multiple, multiple,\
+ multiple, neon_move<q>, fmov")
+@@ -1004,18 +979,10 @@
+ (and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w,0")
+ (match_operand:VDQ_I 2 "aarch64_reg_or_bic_imm" "w,Db")))]
+ "TARGET_SIMD"
+- {
+- switch (which_alternative)
+- {
+- case 0:
+- return "and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
+- case 1:
+- return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,
+- AARCH64_CHECK_BIC);
+- default:
+- gcc_unreachable ();
+- }
+- }
++ "@
++ and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>
++ * return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,\
++ AARCH64_CHECK_BIC);"
+ [(set_attr "type" "neon_logic<q>")]
+ )
+
+@@ -1025,18 +992,10 @@
+ (ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w,0")
+ (match_operand:VDQ_I 2 "aarch64_reg_or_orr_imm" "w,Do")))]
+ "TARGET_SIMD"
+- {
+- switch (which_alternative)
+- {
+- case 0:
+- return "orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
+- case 1:
+- return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,
+- AARCH64_CHECK_ORR);
+- default:
+- gcc_unreachable ();
+- }
+- }
++ "@
++ orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>
++ * return aarch64_output_simd_mov_immediate (operands[2], <bitsize>,\
++ AARCH64_CHECK_ORR);"
+ [(set_attr "type" "neon_logic<q>")]
+ )
+
+diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
+index c0cc91756..7454a5c77 100644
+--- a/gcc/config/aarch64/aarch64.md
++++ b/gcc/config/aarch64/aarch64.md
+@@ -1198,36 +1198,18 @@
+ (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m,m,rZ,w,w,rZ,w"))]
+ "(register_operand (operands[0], <MODE>mode)
+ || aarch64_reg_or_zero (operands[1], <MODE>mode))"
+-{
+- switch (which_alternative)
+- {
+- case 0:
+- return "mov\t%w0, %w1";
+- case 1:
+- return "mov\t%w0, %1";
+- case 2:
+- return aarch64_output_scalar_simd_mov_immediate (operands[1],
+- <MODE>mode);
+- case 3:
+- return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1]);
+- case 4:
+- return "ldr<size>\t%w0, %1";
+- case 5:
+- return "ldr\t%<size>0, %1";
+- case 6:
+- return "str<size>\t%w1, %0";
+- case 7:
+- return "str\t%<size>1, %0";
+- case 8:
+- return TARGET_SIMD ? "umov\t%w0, %1.<v>[0]" : "fmov\t%w0, %s1";
+- case 9:
+- return TARGET_SIMD ? "dup\t%0.<Vallxd>, %w1" : "fmov\t%s0, %w1";
+- case 10:
+- return TARGET_SIMD ? "dup\t%<Vetype>0, %1.<v>[0]" : "fmov\t%s0, %s1";
+- default:
+- gcc_unreachable ();
+- }
+-}
++ "@
++ mov\t%w0, %w1
++ mov\t%w0, %1
++ * return aarch64_output_scalar_simd_mov_immediate (operands[1], <MODE>mode);
++ * return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1]);
++ ldr<size>\t%w0, %1
++ ldr\t%<size>0, %1
++ str<size>\t%w1, %0
++ str\t%<size>1, %0
++ * return TARGET_SIMD ? \"umov\t%w0, %1.<v>[0]\" : \"fmov\t%w0, %s1\";
++ * return TARGET_SIMD ? \"dup\t%0.<Vallxd>, %w1\" : \"fmov\t%s0, %w1\";
++ * return TARGET_SIMD ? \"dup\t%<Vetype>0, %1.<v>[0]\" : \"fmov\t%s0, %s1\";"
+ ;; The "mov_imm" type for CNT is just a placeholder.
+ [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4,
+ store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup")
+--
+2.33.0
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-24 16:52:12 +0000