1 files changed, 103 insertions, 0 deletions
diff --git a/0207-Backport-SME-aarch64-Add-a-register-class-for-w12-w1.patch b/0207-Backport-SME-aarch64-Add-a-register-class-for-w12-w1.patch
new file mode 100644
index 0000000..3d69ca5
--- /dev/null
+++ b/0207-Backport-SME-aarch64-Add-a-register-class-for-w12-w1.patch
@@ -0,0 +1,103 @@
+From 9866b4c1d85d88fd9e25ff3ac5224b69d4e0f0b2 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 5 Dec 2023 10:11:26 +0000
+Subject: [PATCH 108/157] [Backport][SME] aarch64: Add a register class for
+ w12-w15
+
+Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=084122adb5792a9c8e7f7876e2c1d59ba80c228b
+
+Some SME instructions use w12-w15 to index ZA.  This patch
+adds a register class for that range.
+
+gcc/
+	* config/aarch64/aarch64.h (W12_W15_REGNUM_P): New macro.
+	(W12_W15_REGS): New register class.
+	(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it.
+	* config/aarch64/aarch64.cc (aarch64_regno_regclass)
+	(aarch64_class_max_nregs, aarch64_register_move_cost): Handle
+	W12_W15_REGS.
+---
+ gcc/config/aarch64/aarch64.cc | 12 +++++++-----
+ gcc/config/aarch64/aarch64.h  |  6 ++++++
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index a6e996c5b..112dfeabb 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -14213,6 +14213,9 @@ aarch64_label_mentioned_p (rtx x)
+ enum reg_class
+ aarch64_regno_regclass (unsigned regno)
+ {
++  if (W12_W15_REGNUM_P (regno))
++    return W12_W15_REGS;
++
+   if (STUB_REGNUM_P (regno))
+     return STUB_REGS;
+ 
+@@ -14577,6 +14580,7 @@ aarch64_class_max_nregs (reg_class_t regclass, machine_mode mode)
+   unsigned int nregs, vec_flags;
+   switch (regclass)
+     {
++    case W12_W15_REGS:
+     case STUB_REGS:
+     case TAILCALL_ADDR_REGS:
+     case POINTER_REGS:
+@@ -16926,13 +16930,11 @@ aarch64_register_move_cost (machine_mode mode,
+   const struct cpu_regmove_cost *regmove_cost
+     = aarch64_tune_params.regmove_cost;
+ 
+-  /* Caller save and pointer regs are equivalent to GENERAL_REGS.  */
+-  if (to == TAILCALL_ADDR_REGS || to == POINTER_REGS
+-      || to == STUB_REGS)
++  /* Trest any subset of POINTER_REGS as though it were GENERAL_REGS.  */
++  if (reg_class_subset_p (to, POINTER_REGS))
+     to = GENERAL_REGS;
+ 
+-  if (from == TAILCALL_ADDR_REGS || from == POINTER_REGS
+-      || from == STUB_REGS)
++  if (reg_class_subset_p (from, POINTER_REGS))
+     from = GENERAL_REGS;
+ 
+   /* Make RDFFR very expensive.  In particular, if we know that the FFR
+diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
+index 89d30b9bf..8b21faf34 100644
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -648,6 +648,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
+    && (REGNO) != R17_REGNUM \
+    && (REGNO) != R30_REGNUM) \
+ 
++#define W12_W15_REGNUM_P(REGNO) \
++  IN_RANGE (REGNO, R12_REGNUM, R15_REGNUM)
++
+ #define FP_REGNUM_P(REGNO)			\
+   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
+ 
+@@ -674,6 +677,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF;
+ enum reg_class
+ {
+   NO_REGS,
++  W12_W15_REGS,
+   TAILCALL_ADDR_REGS,
+   STUB_REGS,
+   GENERAL_REGS,
+@@ -698,6 +702,7 @@ enum reg_class
+ #define REG_CLASS_NAMES				\
+ {						\
+   "NO_REGS",					\
++  "W12_W15_REGS",				\
+   "TAILCALL_ADDR_REGS",				\
+   "STUB_REGS",					\
+   "GENERAL_REGS",				\
+@@ -719,6 +724,7 @@ enum reg_class
+ #define REG_CLASS_CONTENTS						\
+ {									\
+   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
++  { 0x0000f000, 0x00000000, 0x00000000 },	/* W12_W15_REGS */	\
+   { 0x00030000, 0x00000000, 0x00000000 },	/* TAILCALL_ADDR_REGS */\
+   { 0x3ffcffff, 0x00000000, 0x00000000 },	/* STUB_REGS */		\
+   { 0x7fffffff, 0x00000000, 0x00000003 },	/* GENERAL_REGS */	\
+-- 
+2.33.0
+