summaryrefslogtreecommitdiff
path: root/0224-Backport-SME-aarch64-Add-V1DI-mode.patch
diff options
context:
space:
mode:
Diffstat (limited to '0224-Backport-SME-aarch64-Add-V1DI-mode.patch')
-rw-r--r--0224-Backport-SME-aarch64-Add-V1DI-mode.patch177
1 files changed, 177 insertions, 0 deletions
diff --git a/0224-Backport-SME-aarch64-Add-V1DI-mode.patch b/0224-Backport-SME-aarch64-Add-V1DI-mode.patch
new file mode 100644
index 0000000..401391c
--- /dev/null
+++ b/0224-Backport-SME-aarch64-Add-V1DI-mode.patch
@@ -0,0 +1,177 @@
+From 21f9190106f8324be42e3e8e0510467386dd68a0 Mon Sep 17 00:00:00 2001
+From: Andrew Carlotti <andrew.carlotti@arm.com>
+Date: Fri, 15 Jul 2022 15:25:53 +0100
+Subject: [PATCH 125/157] [Backport][SME] aarch64: Add V1DI mode
+
+Reference: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5ba864c5d11a1c20891a1e054cb7814ec23de5c9
+
+We already have a V1DF mode, so this makes the vector modes more consistent.
+
+Additionally, this allows us to recognise uint64x1_t and int64x1_t types given
+only the mode and type qualifiers (e.g. in aarch64_lookup_simd_builtin_type).
+
+gcc/ChangeLog:
+
+ * config/aarch64/aarch64-builtins.cc
+ (v1di_UP): Add V1DI mode to _UP macros.
+ * config/aarch64/aarch64-modes.def (VECTOR_MODE): Add V1DI mode.
+ * config/aarch64/aarch64-simd-builtin-types.def: Use V1DI mode.
+ * config/aarch64/aarch64-simd.md
+ (vec_extractv2dfv1df): Replace with...
+ (vec_extract<mode><V1half>): ...this.
+ * config/aarch64/aarch64.cc
+ (aarch64_classify_vector_mode): Add V1DI mode.
+ * config/aarch64/iterators.md
+ (VQ_2E, V1HALF, V1half): New.
+ (nunits): Add V1DI mode.
+---
+ gcc/config/aarch64/aarch64-builtins.cc | 1 +
+ gcc/config/aarch64/aarch64-modes.def | 1 +
+ gcc/config/aarch64/aarch64-simd-builtin-types.def | 6 +++---
+ gcc/config/aarch64/aarch64-simd.md | 14 +++++++-------
+ gcc/config/aarch64/aarch64.cc | 2 +-
+ gcc/config/aarch64/iterators.md | 14 ++++++++++++--
+ 6 files changed, 25 insertions(+), 13 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 015e9d975..37bb3af48 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -55,6 +55,7 @@
+ #define v2si_UP E_V2SImode
+ #define v2sf_UP E_V2SFmode
+ #define v1df_UP E_V1DFmode
++#define v1di_UP E_V1DImode
+ #define di_UP E_DImode
+ #define df_UP E_DFmode
+ #define v16qi_UP E_V16QImode
+diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def
+index 8fa66fdb3..dd74da4b3 100644
+--- a/gcc/config/aarch64/aarch64-modes.def
++++ b/gcc/config/aarch64/aarch64-modes.def
+@@ -70,6 +70,7 @@ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */
+ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */
+ VECTOR_MODES (FLOAT, 8); /* V2SF. */
+ VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */
++VECTOR_MODE (INT, DI, 1); /* V1DI. */
+ VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */
+ VECTOR_MODE (FLOAT, HF, 2); /* V2HF. */
+
+diff --git a/gcc/config/aarch64/aarch64-simd-builtin-types.def b/gcc/config/aarch64/aarch64-simd-builtin-types.def
+index 248e51e96..405455814 100644
+--- a/gcc/config/aarch64/aarch64-simd-builtin-types.def
++++ b/gcc/config/aarch64/aarch64-simd-builtin-types.def
+@@ -24,7 +24,7 @@
+ ENTRY (Int16x8_t, V8HI, none, 11)
+ ENTRY (Int32x2_t, V2SI, none, 11)
+ ENTRY (Int32x4_t, V4SI, none, 11)
+- ENTRY (Int64x1_t, DI, none, 11)
++ ENTRY (Int64x1_t, V1DI, none, 11)
+ ENTRY (Int64x2_t, V2DI, none, 11)
+ ENTRY (Uint8x8_t, V8QI, unsigned, 11)
+ ENTRY (Uint8x16_t, V16QI, unsigned, 12)
+@@ -32,7 +32,7 @@
+ ENTRY (Uint16x8_t, V8HI, unsigned, 12)
+ ENTRY (Uint32x2_t, V2SI, unsigned, 12)
+ ENTRY (Uint32x4_t, V4SI, unsigned, 12)
+- ENTRY (Uint64x1_t, DI, unsigned, 12)
++ ENTRY (Uint64x1_t, V1DI, unsigned, 12)
+ ENTRY (Uint64x2_t, V2DI, unsigned, 12)
+ ENTRY (Poly8_t, QI, poly, 9)
+ ENTRY (Poly16_t, HI, poly, 10)
+@@ -42,7 +42,7 @@
+ ENTRY (Poly8x16_t, V16QI, poly, 12)
+ ENTRY (Poly16x4_t, V4HI, poly, 12)
+ ENTRY (Poly16x8_t, V8HI, poly, 12)
+- ENTRY (Poly64x1_t, DI, poly, 12)
++ ENTRY (Poly64x1_t, V1DI, poly, 12)
+ ENTRY (Poly64x2_t, V2DI, poly, 12)
+ ENTRY (Float16x4_t, V4HF, none, 13)
+ ENTRY (Float16x8_t, V8HF, none, 13)
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 62493cdfa..04592fc90 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -8326,16 +8326,16 @@
+ })
+
+ ;; Extract a single-element 64-bit vector from one half of a 128-bit vector.
+-(define_expand "vec_extractv2dfv1df"
+- [(match_operand:V1DF 0 "register_operand")
+- (match_operand:V2DF 1 "register_operand")
++(define_expand "vec_extract<mode><V1half>"
++ [(match_operand:<V1HALF> 0 "register_operand")
++ (match_operand:VQ_2E 1 "register_operand")
+ (match_operand 2 "immediate_operand")]
+ "TARGET_SIMD"
+ {
+- /* V1DF is rarely used by other patterns, so it should be better to hide
+- it in a subreg destination of a normal DF op. */
+- rtx scalar0 = gen_lowpart (DFmode, operands[0]);
+- emit_insn (gen_vec_extractv2dfdf (scalar0, operands[1], operands[2]));
++ /* V1DI and V1DF are rarely used by other patterns, so it should be better
++ to hide it in a subreg destination of a normal DI or DF op. */
++ rtx scalar0 = gen_lowpart (<VHALF>mode, operands[0]);
++ emit_insn (gen_vec_extract<mode><Vhalf> (scalar0, operands[1], operands[2]));
+ DONE;
+ })
+
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index b8e540b6e..f7285555b 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -4117,7 +4117,7 @@ aarch64_classify_vector_mode (machine_mode mode)
+ case E_V8QImode:
+ case E_V4HImode:
+ case E_V2SImode:
+- /* ...E_V1DImode doesn't exist. */
++ case E_V1DImode:
+ case E_V4HFmode:
+ case E_V4BFmode:
+ case E_V2SFmode:
+diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
+index 152d28f6b..94db8c53f 100644
+--- a/gcc/config/aarch64/iterators.md
++++ b/gcc/config/aarch64/iterators.md
+@@ -138,6 +138,9 @@
+ ;; VQ without 2 element modes.
+ (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF])
+
++;; 2 element quad vector modes.
++(define_mode_iterator VQ_2E [V2DI V2DF])
++
+ ;; BFmode vector modes.
+ (define_mode_iterator VBF [V4BF V8BF])
+
+@@ -1116,12 +1119,13 @@
+ (define_mode_attr nunits [(V8QI "8") (V16QI "16")
+ (V4HI "4") (V8HI "8")
+ (V2SI "2") (V4SI "4")
+- (V2DI "2") (V8DI "8")
++ (V1DI "1") (V2DI "2")
+ (V4HF "4") (V8HF "8")
+ (V4BF "4") (V8BF "8")
+ (V2SF "2") (V4SF "4")
+ (V1DF "1") (V2DF "2")
+- (DI "1") (DF "1")])
++ (DI "1") (DF "1")
++ (V8DI "8")])
+
+ ;; Map a mode to the number of bits in it, if the size of the mode
+ ;; is constant.
+@@ -1501,6 +1505,12 @@
+ (V2DI "di") (V2SF "sf")
+ (V4SF "v2sf") (V2DF "df")])
+
++;; Single-element half modes of quad vector modes.
++(define_mode_attr V1HALF [(V2DI "V1DI") (V2DF "V1DF")])
++
++;; Single-element half modes of quad vector modes, in lower-case
++(define_mode_attr V1half [(V2DI "v1di") (V2DF "v1df")])
++
+ ;; Double modes of vector modes.
+ (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
+ (V4HF "V8HF") (V4BF "V8BF")
+--
+2.33.0
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-24 14:59:00 +0000