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From d10807504a7f4e58a7dd1fa245d0ccf16227d222 Mon Sep 17 00:00:00 2001
From: Chernonog Viacheslav <chernonog.vyacheslav@huawei.com>
Date: Wed, 4 Dec 2024 20:07:23 +0800
Subject: [PATCH] [Bugfix] replace tmp pattern split
move split before reload
change split tmp pattern to 3 instructions
---
gcc/config/aarch64/aarch64-simd.md | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 04592fc90..fb5e355d0 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -6566,18 +6566,25 @@
(match_operand:VDQHSD 1 "register_operand" "w")
(match_operand:VDQHSD 2 "half_size_minus_one_operand"))
(match_operand:VDQHSD 3 "cmlt_arith_mask_operand")))]
- "TARGET_SIMD && flag_cmlt_arith"
+ "TARGET_SIMD && !reload_completed && flag_cmlt_arith"
"#"
- "&& reload_completed"
- [(set (match_operand:<V_INT_EQUIV> 0 "register_operand")
+ "&& true"
+ [(set (match_operand:<V_INT_EQUIV> 0 "register_operand" "=w")
(lshiftrt:<V_INT_EQUIV>
(match_operand:VDQHSD 1 "register_operand")
(match_operand:VDQHSD 2 "half_size_minus_one_operand")))
+ (set (match_operand:<V_INT_EQUIV> 4 "register_operand" "w")
+ (match_operand:VDQHSD 3 "cmlt_arith_mask_operand"))
(set (match_dup 0)
(and:<V_INT_EQUIV>
- (match_dup 0)
- (match_operand:VDQHSD 3 "cmlt_arith_mask_operand")))]
- ""
+ (match_dup 4)
+ (match_dup 0)))]
+ {
+ if (can_create_pseudo_p ())
+ operands[4] = gen_reg_rtx (<V_INT_EQUIV>mode);
+ else
+ FAIL;
+ }
[(set_attr "type" "neon_compare_zero")]
)
--
2.33.0
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