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| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | python-slvcodec.spec | 93 | ||||
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@@ -0,0 +1 @@ +/slvcodec-0.4.17.tar.gz diff --git a/python-slvcodec.spec b/python-slvcodec.spec new file mode 100644 index 0000000..eb74b14 --- /dev/null +++ b/python-slvcodec.spec @@ -0,0 +1,93 @@ +%global _empty_manifest_terminate_build 0 +Name: python-slvcodec +Version: 0.4.17 +Release: 1 +Summary: Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. +License: MIT +URL: https://github.com/benreynwar/slvcodec +Source0: https://mirrors.aliyun.com/pypi/web/packages/09/87/b5f51d0575f5a14eda42a61fdd8ed8bb2fcb426fca02cc8f02cde8b443f5/slvcodec-0.4.17.tar.gz +BuildArch: noarch + +Requires: python3-jinja2 +Requires: python3-pytest +Requires: python3-vunit-hdl +Requires: python3-pyyaml +Requires: python3-cocotb +Requires: python3-fusesoc + +%description +slvcodec is a tool that analyzes VHDL and generates: + * Functions to convert arbitrary VHDL types to and from std_logic_vector. + * Generate testbenches for entities that read inputs from a file, and + write outputs to a file. + * Utilities so that unit tests for VHDL code can easily to be written + in python. + +%package -n python3-slvcodec +Summary: Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. +Provides: python-slvcodec +BuildRequires: python3-devel +BuildRequires: python3-setuptools +BuildRequires: python3-pip +%description -n python3-slvcodec +slvcodec is a tool that analyzes VHDL and generates: + * Functions to convert arbitrary VHDL types to and from std_logic_vector. + * Generate testbenches for entities that read inputs from a file, and + write outputs to a file. + * Utilities so that unit tests for VHDL code can easily to be written + in python. + +%package help +Summary: Development documents and examples for slvcodec +Provides: python3-slvcodec-doc +%description help +slvcodec is a tool that analyzes VHDL and generates: + * Functions to convert arbitrary VHDL types to and from std_logic_vector. + * Generate testbenches for entities that read inputs from a file, and + write outputs to a file. + * Utilities so that unit tests for VHDL code can easily to be written + in python. + +%prep +%autosetup -n slvcodec-0.4.17 + +%build +%py3_build + +%install +%py3_install +install -d -m755 %{buildroot}/%{_pkgdocdir} +if [ -d doc ]; then cp -arf doc %{buildroot}/%{_pkgdocdir}; fi +if [ -d docs ]; then cp -arf docs %{buildroot}/%{_pkgdocdir}; fi +if [ -d example ]; then cp -arf example %{buildroot}/%{_pkgdocdir}; fi +if [ -d examples ]; then cp -arf examples %{buildroot}/%{_pkgdocdir}; fi +pushd %{buildroot} +if [ -d usr/lib ]; then + find usr/lib -type f -printf "\"/%h/%f\"\n" >> filelist.lst +fi +if [ -d usr/lib64 ]; then + find usr/lib64 -type f -printf "\"/%h/%f\"\n" >> filelist.lst +fi +if [ -d usr/bin ]; then + find usr/bin -type f -printf "\"/%h/%f\"\n" >> filelist.lst +fi +if [ -d usr/sbin ]; then + find usr/sbin -type f -printf "\"/%h/%f\"\n" >> filelist.lst +fi +touch doclist.lst +if [ -d usr/share/man ]; then + find usr/share/man -type f -printf "\"/%h/%f.gz\"\n" >> doclist.lst +fi +popd +mv %{buildroot}/filelist.lst . +mv %{buildroot}/doclist.lst . + +%files -n python3-slvcodec -f filelist.lst +%dir %{python3_sitelib}/* + +%files help -f doclist.lst +%{_docdir}/* + +%changelog +* Tue Jun 20 2023 Python_Bot <Python_Bot@openeuler.org> - 0.4.17-1 +- Package Spec generated @@ -0,0 +1 @@ +a84cc13f1da2030eed462be4a54e9ab7 slvcodec-0.4.17.tar.gz |